The present invention relates generally to a technique for reducing power consumption by a processor, and more particularly to such a technique for reducing power consumption by allowing clock speed of the processor to be varied.
Computers, particularly personal computers, have been widely used not only in enterprises but also in homes and schools. The performance of microprocessors used in the personal computers has been enhanced dramatically, and it is not unusual for the operating clock to exceed 1 GHz today. As the operating clock increases, however, both power consumption and heating increase, and a problem to be solved for high speed microprocessors is how to suppress such power consumption and heating. Notebook computers in particular are operated with battery power, and reducing power consumption is therefore even more important with notebook computers than with desktop computers.
In view of the above, some techniques have been proposed to vary a clock speed of a processor to reduce power consumption and heating in the processor. Such proposals are based on the understanding that not all programs need to run at the same clock speed. Japanese Patent Publication H8-76874, for example, teaches a CPU clock control device and method for which one or more performance information setting circuits for setting CPU performance information required for each task, a selection information generating circuit for determining the clock frequency of the CPU so that the CPU operates at the minimum performance level required by a task started, an oscillation circuit for generating a plurality of clock signals, and a clock selecting circuit for selecting one of the clock signals and providing it to the CPU. This clock control is aimed at operating the CPU with low power consumption even at the time of task execution in a multitasking environment depending on a program to be executed in the CPU, by switching automatically to the slowest CPU clock at which performance requirement of a program to be executed is satisfied to thereby reduce power consumption.
U.S. Pat. No. 6,138,232 (Japanese Patent Publication H10-228383) teaches a microprocessor and operating method therefor in which an interrupt from one of a plurality of interrupt sources is accepted to change from operating on a current task to operating on a priority task, and a rate of microprocessor instruction operation during operation in response to an interrupt is set depending upon the interrupt source producing the interrupt. According to this teaching, a rate table of interrupt source to instruction operation is provided, which is accessed upon receipt of an interrupt to obtain a rate of instruction operation corresponding to the interrupt source.
As seen from the above, the prior art has sought reduction of power consumption and heating by changing the operating speed (clock) of a processor depending on a task to be executed or a type of interrupt to be processed.
The conventional techniques change the clock speed based on a predetermined task or interrupt, which may not achieve optimum operation in the case where a task comprises a mixture of codes some of which require high speed operation while the other can run at a slower speed. In order to achieve the optimum operation aiming at the reduction of power consumption and heating, more sophisticated control, specifically based on an execution address and hence execution code of a program is required.